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jjac705's avatar
jjac705
Icon for New Contributor rankNew Contributor
3 years ago

SoC EDS issue

Hi, I attempted the SoC EDS as per the pdf SoC_software_lab_16.0.pdf on rocketboards.org. I was asked to see the link to create a u-boot-socfpga. In that, it was told to clone a github file which ...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi jjac705,


There were some changes on the software build handling from older to newer Quartus version. I recommend to use the newer Quartus build process in order to get a better support.

By the way I do not understand the last part of your question "to justify a 32-bit output of a VHDL program in Cyclone V using Quartus." Can elaborate more if possible.


Thanks.

Regards,

Aik Eu