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jjac705
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3 years ago

SoC EDS issue

Hi, I attempted the SoC EDS as per the pdf SoC_software_lab_16.0.pdf on rocketboards.org. I was asked to see the link to create a u-boot-socfpga. In that, it was told to clone a github file which ...
jjac705's avatar
jjac705
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3 years ago

Hi Aik Eu,

I ma struggling with HPS platform in Cyclone V SoC. I attempted to do it in Quartus 17.1,19.1 and 20.1 and I get stuck in each of them. I put forth another question based on SoC EDS 20.1 ( https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Cannot-complete-the-linaro-part/m-p/1446947/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExDWTdNOFpNVVlFOVpWfDE0NDY5NDd8U1VCU0NSSVBUSU9OU3xoSw#M23889) where I followed this link https://www.rocketboards.org/foswiki/Documentation/SoCEDS#Install_SoC_EDS_AN1.

Honestly very very clueless regarding this matter. It seems like in every version there are some drastic changes made and being a beginner in this matter, things get very confusing. I just need to know how to configure the ARM processor in Cyclone V as this issue has been affecting my project dearly. Else I just want to know if there is any other way to justify a 32-bit output of a VHDL program in Cyclone V using Quartus.

Do let me know.

Thanking You

Yours Sincerely

Jerry Jacob