Forum Discussion
adrianf0
New Contributor
7 years agoSDRAM Controller bug: missed data word
I have a project (attachment) using an open source 32-bit RISC-V processor connected in Qsys through 32-bit AXI bus and SDRAM Controller (v 18.1) to 16-bit SDRAM memory. Due to width mismatch, each A...
adrianf0
New Contributor
7 years agoI am surprised by your reply. Why did you link me with the implementation of military, defense intelligence, nuclear/biochemical or space products? If you can't support my problem, because somebody else could misuse it, then it questions the existence of this forum at all.
Finally, what is the official channel, for clients who bought and use your devices and tools (Lite edition), debugged your core and would like to report a potential bug (pointing explicitly to the suspected signal causing the problem on top of that)?