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adrianf0's avatar
adrianf0
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6 years ago

SDRAM Controller bug: missed data word

I have a project (attachment) using an open source 32-bit RISC-V processor connected in Qsys through 32-bit AXI bus and SDRAM Controller (v 18.1) to 16-bit SDRAM memory. Due to width mismatch, each A...
BoonT_Intel's avatar
BoonT_Intel
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6 years ago
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  • adrianf0's avatar
    adrianf0
    Icon for New Contributor rankNew Contributor
    6 years ago

    @BoonT_Intel​ : I received a private message from you, advising me to contact a local distributor from whom the devices were bought. Unfortunately, they don't have a field application engineer which could support us with this case. I informed you about that by a private message asking for further support, however, I haven't received any reply in the last two weeks.