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adrianf0
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6 years ago

SDRAM Controller bug: missed data word

I have a project (attachment) using an open source 32-bit RISC-V processor connected in Qsys through 32-bit AXI bus and SDRAM Controller (v 18.1) to 16-bit SDRAM memory. Due to width mismatch, each A...
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adrianf0
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6 years ago

Dear BCT_Intel,

It's a regular Synchronous DRAM (IS42VM16160K-75BLI). However, I enclosed the full project to my original post, so you can easily check the configuration and the Avalon-MM to AXI bridge connection. Moreover, I pointed directly the cause of the problem already. Unfortunately, I can't invest more time in debugging the bug (apparently) of the Intel IP core. I expect it will be fixed soon as it's critical in my project.