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adrianf0
New Contributor
New ContributorSDRAM Controller bug: missed data word
I have a project (attachment) using an open source 32-bit RISC-V processor connected in Qsys through 32-bit AXI bus and SDRAM Controller (v 18.1) to 16-bit SDRAM memory. Due to width mismatch, each A...
BoonT_Intel
Frequent Contributor
Frequent ContributorAlso see if this statement is match with your observation:
If the master data width is wider than the slave data width, words in the master address space map to multiple locations in the slave address space. For example, a 32-bit master read from a 16-bit slave results in two read transfers on the slave side. The reads are to consecutive addresses.
