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adrianf0's avatar
adrianf0
Icon for New Contributor rankNew Contributor
6 years ago

SDRAM Controller bug: missed data word

I have a project (attachment) using an open source 32-bit RISC-V processor connected in Qsys through 32-bit AXI bus and SDRAM Controller (v 18.1) to 16-bit SDRAM memory. Due to width mismatch, each A...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Dear Sir,

Which SDRAM protocol that you are using (DDR3, DDR4)? As per my understanding, the EMIF IP used in Intel FPGA are access using Avalon-MM bridge instead of AXI bridge. Can you also signaltap the Avalon-MM bridge and see if the issue really occur from the IP AMM port?