Forum Discussion
adrianf0
New Contributor
New ContributorSDRAM Controller bug: missed data word
I have a project (attachment) using an open source 32-bit RISC-V processor connected in Qsys through 32-bit AXI bus and SDRAM Controller (v 18.1) to 16-bit SDRAM memory. Due to width mismatch, each A...
BoonT_Intel
Frequent Contributor
Frequent ContributorDear Sir,
Which SDRAM protocol that you are using (DDR3, DDR4)? As per my understanding, the EMIF IP used in Intel FPGA are access using Avalon-MM bridge instead of AXI bridge. Can you also signaltap the Avalon-MM bridge and see if the issue really occur from the IP AMM port?
