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SZai0's avatar
SZai0
Icon for New Contributor rankNew Contributor
6 years ago

Reset bridge removed in code

Hi, we need to utilize the FPGA to HPS SDRAM connect in our u-boot Linux condition. We utilize the Altera u-boot-socfpga uboot. Each first time the piece hangs/crashes, on the off chance that we ...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

May I know which Device you are working on? Cyclone V, Arria 10 SoC etc.? Which Quartu/SoC EDS version is used in your compilation?

Did you able to get the uboot logs of the reported error?

If so, can you provide the screenshot or whichever is convenient to you the boot logs for both of the first time and the after warm reset logs?