Memory Tests for Arria 10 FPGA

Hi Karthik, The link provided is not related to DDR. I suggest you to generate the synthesis example design which contain a traffic generator to test the memory and signal an overall pass or fail status of your DDR. You can refer to “Chapter 13: Functional Description—Example Designs” of this EMIF handbook for more details on how to generate the example design and how the traffic generator works. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf I sincerely hope this helps. Thanks Regards, NAli1