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Humusk
New Contributor
New ContributorMAX 10 RGMII interface - PLL input from non-dedicated clock pin
Hello, I'm trying to create my own RGMII interface for the MAX 10 Development Kit. Until now I was working with the Cyclone 10 LP Evaluation Kit, I sucesfully created an RGMII following this intel ...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
I think you might have posted this thread into the wrong community forum. This forum only covers Intel FPGA product. Our agents can only help to provide assistance with regards to FPGA product. If you have further enquiries on other Intel product, please post your question to the correct Intel Community topics from the link below:
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We will then require deleting this thread from the Intel FPGA forum topic. Thank you.
