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Humusk's avatar
Humusk
Icon for New Contributor rankNew Contributor
7 years ago

MAX 10 RGMII interface - PLL input from non-dedicated clock pin

Hello, I'm trying to create my own RGMII interface for the MAX 10 Development Kit. Until now I was working with the Cyclone 10 LP Evaluation Kit, I sucesfully created an RGMII following this intel ...
Mike_Intel's avatar
Mike_Intel
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hello Humusk, Thank you for the clarifications, Regarding your inquiry, it is best if you create another thread in our FPGA topic. They should help you further with your inquiry. https://forums.intel.com/s/ If you have questions, please let us know. Best regards, Michael L. Intel Customer Support Under Contract to Intel Corporation