MAX 10 RGMII interface - PLL input from non-dedicated clock pin

Hello, sorry for my delay in answering.

I'm working with a MAX10 FPGA embeded in Intel's Development Board, this board is connected to a switch. The Ethernet interface is a custom interface inside the FPGA that uses de board RGMII. It is working in another board but not with this one. I think that the best solution will be to implement an MDIO an modify the RGMII delays, but i'm having difficulties finding the registers of the RGMII. The physical RGMII that your board uses is the 88E1111, but the datasheet is under NDA.

Thanks,

Gerard.