Intel® Stratix® 10 L- and H-Tile Transceiver PHYの使い方について

Hi,

Thank you very much for your help in the translation.

Please see my responses as following:

Q1. According to the user manual, I think that to assert signal "rx_is_lockedtodata", it's necessary to receive some toggled signal from link partner by rx_serial_data. Otherwise, the reset would not end and signal "phystatus" would not be de-asserted. Is my understanding correct?

[CP] Yes, your understanding is correct. The RX need to received toggling data from link partner before the CDR can achieve lock-to-data and assert rx_is_lockedtodata.

Q2. To finish the reset of PCIe phy, the Phy in Host-side must finish its reset before Local-side does, otherwise the Host-side can not transmit toggled signal to Local side. In case that I connect 2 stratix10 PCIe phys as Local and Host, I think I should consider a method to transmit data to each other within their reset period. Is that correct?

[CP] Yes, your understand is corret. You would need to send some toggling signal to Local before it can achieve CDR lock-to-data. Else, it will continue to wait and rx_digitalreset will remain asserted.

Please feel free to let me know if you would like to further engage our PCIe expert to provide further guidance on the PCIe link up. If yes, you may help to create a new Forum case and let me know the number so that I can help to route. I am unable to duplicate case from this probably due to access limitation.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin