HPS to FPGA bridge in GSRD Agilex 7 m-series

Hi Ihsan28,

in order to test the bridges, you may need information on the addresses.

For quick answer, you can find them in

https://www.intel.com/content/www/us/en/programmable/hps/agilex7/hps.html

The bridge addresses are

With these addresses, you can access the bridges via "md" or "mw" in uboot or "devmem2" in linux.

There is also the FPGA to HPS bridge (last one in the table above). This can be accessed via system console.

Refer: https://www.intel.com/content/www/us/en/docs/programmable/683819/current/analyzing-and-debugging-designs-with-84752.html

These are the details, about how the software driver gets the address 0xF9001080 for the LED.

After following the steps here:

https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/#build-hardware-design

You can find ghrd_agfb027r24c2e2v.qpf and qsys_top.qsys in the agilex_soc_devkit_ghrd.

These can be used to open the project in Platform Designer.

By default, GHRD enables all HPS bridges.

You can find more information for the HPS Parameters for bridges here:

https://www.intel.com/content/www/us/en/docs/programmable/683581/current/hps-fpga-axi-bridges.html

You also can check where the bridges connected to via the Agilex HPS IP.

Tracing down to h2f_lw_axi_master, the address offset for the pipeline bridge is 0x1000.

Through the pipeline bridge, the PIO IP (led_pio) that controls LEDs has address offset of 0x80.

0xF9000000 + 0x1000 + 0x80 = 0xF9001080

Regards,

shun jing