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Rainwang's avatar
Rainwang
Icon for Contributor rankContributor
3 years ago

how to use separated the FPGA configuration and HPS booting?

As below figure shows, we use the 10AS016 chip, and we have 2 EPCQ flashes on our board, one for HPS booting and the other for FPGA configuration. We stored the FPGA configure file in the FPGA side E...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Okay, can you see the below logs, below logs shown that the first two initial logs where it needs an FPGA configuration done before booting the SPL, after the two initial logs, the FPGA is programmed successfully using Quartus Programmer, you can see the U-boot SPL loading and go into U-boot user mode, did you see this behavior? Does this fits your design requirement?:


U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Trying to boot from SPI

QSPI: Invalid input arguments txlen 64

SPL: failed to boot from all boot devices

### ERROR ### Please RESET the board ###

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Trying to boot from SPI

QSPI: Invalid input arguments txlen 64

SPL: failed to boot from all boot devices

### ERROR ### Please RESET the board ###

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

DDRCAL: Success

DDRCAL: Scrubbing ECC RAM (1024 MiB).

DDRCAL: SDRAM-ECC initialized success with 146 ms

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Trying to boot from SPI

U-Boot 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)socfpga_arria10

CPU: Altera SoCFPGA Arria 10

BOOT: QSPI Flash (1.8V)

Model: Altera SOCFPGA Arria 10

DRAM: 1 GiB

Core: 69 devices, 16 uclasses, devicetree: separate

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Loading Environment from SPIFlash... SF: Detected mt25qu01g with page size 256 Bytes, erase size 4 KiB, total 128 MiB

*** Warning - bad CRC, using default environment

In: serial

Out: serial

Err: serial

Model: Altera SOCFPGA Arria 10

Net:

Warning: ethernet@ff800000 (eth0) using random MAC address - 52:6c:4d:8d:5c:15

eth0: ethernet@ff800000

Hit any key to stop autoboot: 0

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