how to use separated the FPGA configuration and HPS booting?

i have no questions on early IO release, I unchecked this option in both HPS EMIF setting of platform designer and the device and pin options of Quartus, as i showed in below images with red highlighted.

my question is just to double confirm with you, per my test, the waiting loop is not in boot ROM and also not in SPL. So for my application, I need to add a wait loop in SPL by myself to let it wait until the FPGA config done, then the booting will jump out from the wait loop and go ahead and we need not trigger the HPS reset again after FPGA config done.

thanks.