Contributor
Regular ContributorHi,
Yes, should be the Boot ROM as the settings set as Early IO release feature being disabled, it will need and keep checking for a Full FPGA config before booting the U-boot SPL, as the A10 does not have preloader.
Yes, we did tried that version and it was performing of what I mentioned previously.
Disclaimer, this feature is not fully tested, so you will need to use it at your own risk, anyway we may be able to give best support on any issue you'd have.
Contributorhi,
today we tested this idea on our system, with the same SPL as HPS booting first then configuration FPGA, but we removed the periph.rbf from the DTB package of SPL. and we programed the FPGA configuration file(the early IO release is disabled) into the EPCQ on FPGA side, and config the FPGA with AS mode.
aftet power up, below information showed.
it seems the booting didn't wait in the boot ROM, it enterred into the SPL.
1. the SPL found FPGA is not configured, then it try to configure the FPGA, but we removed the periph.rbf from the DTB so it can not find the rbf file.
2. after FPGA AS configuration completed, as i mentioned, i connected the FPGA_INIT_DONE to the HPS_RST, then it trigger a cold reset, the HPS reset again, this time it found that the FPGA is configured and it go ahead to calibrate the DDR, run u-boot.......all OK.
3. from above info, it seems no wait loop in the boot ROM for waiting the FPGA config done. it still jump into the SPL step.
4. if 3 is right, I think the next step is, we need to add wait loop in SPL to wait for FPGA config done, with this, we need not connect the FPGA_INIT_DONE to the HPS_RST to trigger a cold reset after FPGA config completed.
thank you
