how to use separated the FPGA configuration and HPS booting?

Hi,

So for your case, you would want the HPS to boot right after the FPGA have been configured, meaning there is a case where the FPGA have to be reset/power cycle?

If for separate boot sequence, the HPS can be a loop state in which it will wait for the FPGA to be configured before it will continue boot to SSBL/U-boot for e.g. So wherever your FPGA is to be configured, Quartus Programmer/HPS flash etc, the HPS will wait for it, only then boot to SSBL/U-boot. Just for this case the HPS will always be running and always wait for the FPGA to be configured and will show the UART terminal log of the "failure of the FPGA not configured" etc.

I believe I have test this on the latest U-boot, no much change needed nor any signal to be set/control, but Early IO Release feature must be disabled in Quartus, is this close to what you're trying to achieve?