Contributor
Regular ContributorHi,
Apologies for the late respond, my reply didn't went through.
First of all just to be clear, the FPGA boot first is not fully supported in our latest U-boot and require manual changes and we cannot confirm if it would work in our latest U-boot. Below is the old design flow:
So for the old design, the FPGA first boot up, and HPS wait after full FPGA config. We have the settings and config in Quartus, the old design (to be use as reference) looks like below:
https://www.rocketboards.org/foswiki/Documentation/UBootA10FPGABoot
With the settings enabled, the FPGA will configure fully first with the FPGA config that have been set in Quartus, or by Quartus Programmer manually.
After full FPGA config is done, then HPS will boot from it's sourced that is selected in Quartus + BSEL pins (flash boot devices).
These should be the flow of it if you are to do FPGA first config with U-boot edits.
As mentioned, the FPGA boot first feature is not fully supported in our latest U-boot for A10.
So all the supported feature and documentation, we recommend users to follow from our official Rocketboards A10 documentation page:
https://www.rocketboards.org/foswiki/Documentation/Arria10SoCGSRD
https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Contributorhi,
Per page 689 of Intel Arria 10 Hard Processor System Technical Reference Manual, there are 3 options for Booting and Configuration Options, as below:
• The HPS boot and FPGA configuration occur separately.
• The HPS boots first and then configures the FPGA.
• The HPS boots from the FPGA after the FPGA is configured.
What I want is the option 1, the HPS boot and FPGA configuration occur separately, not the option 3. I checked the link you gave and it seems related to the option 3. We currently realized the option 2, and in option 2 the FPGA image shall be stored in HPS side EPCQ flash, we can not use the RSU IP to manage it. but as i mentioned, i want to store the FPGA image into FPGA side EPCQ so that i can use RSU IP to manage our factory image and app image (and we also need to upgrade the app image in system, this feature can also be supported by RSU).
If currently u-boot version can not support option 1, we can change it. but my question is, in option 1, even the booting and FPGA configuration occur separately, there is dependency between them. If the HPS booting runs to u-boot step and need to use the DDR, but at this time the FPGA configuration have not been done and the DDR have not been brought up, then the HPS booting shall be fail, right? To avoid this, how to control the HPS booting start after the FPGA configration done? Shall we need to connect the FPGA_init_done signal to HPS_RST pin so that the HPS booting can be triggered again after the FPGA configuation completed? Or if you have any example or document for option 1, please share to me.
Very appriciated.
Contributorwill you please check my latest question and help to answer it? thanks.
