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TLie0
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7 years ago

How to make Intel FPGA starter edition 10.5b to display systemverilog unpacked array?

I am in the middle of trying out Intel FPGA starter edition 10.5b, however I can not get modelsim to display my unpacked array signal in the systemverilog. The simulation works fine but vsim does not...
TLie0's avatar
TLie0
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7 years ago

Thank you Vicky!

I managed to get support from Mentor and found out what the issue is.

I normally uses wild character * to log everything. This somehow does not work with unpacked array. I have to individually log them one by one in order to debug them in the waveform (when running simulation in command line)