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sujan19's avatar
sujan19
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4 months ago

How to customize the Agilex 7 I-series OS build with SOF and HPS changes ?

Hi Team, So we are working with Agilex 7 I-series Evaluation kit, We have successfully built yocto image for the GSRD as explained in this guide : https://altera-fpga.github.io/rel-24.3.1/embedded...
Fpga Devkit
tehjingy_Altera's avatar
tehjingy_Altera
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4 months ago

Hi


You could take a look at the link below for the GSRD for the Agilex7 I series devkit.

https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/


Please find the answers below:

1.Apart from the SOF file, what other file needs be generated from Quartus Prime ?

For sof it is a volatile configuration. For a non-volatile configuration you would need the RBF or JIC format.


2.Where is the dts, which we can customize for HPS & FPGA-HPS ?

For the Agilex7 you could find the device tree here:

https://github.com/altera-fpga/linux-socfpga/tree/socfpga-6.12.11-lts/arch/arm64/boot/dts/intel


3.What's the build flow for such a customized design. Since the guide only explains about the GSRD, Can you explain the flow for custom designs ?

You could refer to the link below for the boot flow:

https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/f-series/soc/boot-examples/ug-linux-boot-agx7-soc/



Regards

Jingyang, Teh


  • sujan19's avatar
    sujan19
    Icon for New Contributor rankNew Contributor
    4 months ago

    Hi Jingyang,

    Thanks for replying.

    You could refer to the link below for the boot flow:

    https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/f-series/soc/boot-examples/ug-linux-boot-agx7-soc/

    1. This Guide for GHRD is for f-series SOC, does this apply for I-series as well?
    2. And correct me if i am wrong, should we use our custom design's SOF file to build the ghrd.hps.jic image in this command : 
    quartus_pfg -c \
agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof \
ghrd.jic \
-o device=MT25QU128 \
-o flash_loader=AGFB014R24B2E2V \
-o hps_path=u-boot-socfpga/spl/u-boot-spl-dtb.hex \
-o mode=ASX4 \
-o hps=1​


    instead of one built by this git repo : https://github.com/altera-opensource/ghrd-socfpga

    • If yes, what other file do we need to generate apart from SOF file to generate .jic and .img files ?
    • We also have this file hps_bootloader_handoff_bringup.bin , what is use of this ? and where is it used ?


    Regards,
    Sujan