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Campbell's avatar
Campbell
Icon for New Contributor rankNew Contributor
5 years ago

FPGA On-Chip Memory Initialization with Preloader

Hello,

I am attempting to boot the Cyclone V from the FPGA on-chip memory however when I try to initialize the on-chip memory component with the preloader.hex file by re-compiling the project in Quartus I get the following error:

Error (114016): Out of memory in module quartus_map.exe (5304 megabytes used)
Error (293007): Current module quartus_map ended unexpectedly. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Intel FPGA website (http://dl.altera.com/requirements/).

I have 16GB of RAM on my computer so memory shouldn't be an issue. I also have ~12GB free on my one hard drive if that makes a difference. I am currently using Quartus Prime version 20.1.1 Build 720 and Intel Embedded Command Shell version 20.1 Build 711. However, when I try to use a different preloader.hex file generated previously using Quartus version 17.0, I do not encounter the error. I am using Windows 10 and because of our licensing I am unable to use an older version of EDS (i.e the old boot flow).

The steps I used to generate the preloader are given below (I was unable to find documentation of the full preloader generation process on Windows, this is what I was able to piece together and get working):

NOTE: I did have to implement multiple fixes to get this working. I can provide more details on this if needed.

Key:

[WSL] run in the WSL terminal (Ubuntu 18.04 LTS)

[ECS] run in the Embedded Command Shell terminal (C:\intelFPGA\20.1\embedded\Embedded_Command_Shell.bat)

1. [ECS], navigate to project directory

2. [ECS] $ mkdir -p software/bootloader

3. [ECS] $ bsp-create-settings --type spl --bsp-dir software/bootloader --preloader-settings-dir hps_isw_handoff/soc_system_hps_0 --settings software/bootloader/settings.bsp

4. make required edits to software/bootloader/settings.bsp

5. [ECS] $ bsp-generate-files --bsp-dir software/bootloader/ --settings software/bootloader/settings.bsp

6. [WSL] navigate to project directory

7. [WSL] $ cd software/bootloader

8. [WSL] $ git clone https://github.com/altera-opensource/u-boot-socfpga

9. [WSL] $ cd u-boot-socfpga

10. [WSL] $ ./arch/arm/mach-socfpga/qts-filter.sh cyclone5 ../../.. .. ./board/terasic/de10-nano/qts

11. [WSL] $ export CROSS_COMPILE=<path to toolchain>/gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf/bin/arm-none-linux-gnueabihf-

12. [WSL] $ make socfpga_de10_nano_defconfig

13. [WSL] $ make -j 24

14. [WSL] $ export PATH=<path to toolchain>/gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf/bin:$PATH

15. [WSL] $ cd ..

16. [WSL] $ arm-none-linux-gnueabihf-objcopy -O ihex --adjust-vma -0xc0000000 u-boot-socfpga/spl/u-boot-spl preloader.hex

If anyone can point out the reason for my error and confirm if my process is correct, I would greatly appreciate it.

Thanks,

Campbell

6 Replies

    • Campbell's avatar
      Campbell
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hello and thank you for your response,

      I understand that the preloader generation process works best on Linux however I would like to carry out the process on Windows if at all possible. I already have a significant amount of the project set up on Windows and I believe it will be easier for people in my organization to follow my design example on Windows.

      Thanks,

      Campbell

      • EBERLAZARE_I_Intel's avatar
        EBERLAZARE_I_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        Hi,

        If you insist on using the Windows environment to build, then you might need to use version 19.1/19.3 to compile and build in Windows.

  • Campbell's avatar
    Campbell
    Icon for New Contributor rankNew Contributor
    5 years ago

    Some updates:

    For some background, for my demo I am simply trying to run the Altera-SoCFPGA-HardwareLib-16550-CV-ARMCC example design on the HPS which ships with Quartus (C:\intelFPGA\20.1\embedded\examples\software). Before building the project, I had to change the toolchain to Arm Compiler 5 (this is the toolchain the project was designed for and it wouldn't build properly otherwise).

    Opening the generated application.axf.objdump file I noticed that Section #5: ARM_LIB_STACKHEAP was very large (1072623568 bytes). To see if this section may have been the cause of the errors, I tried to remove this section while generating the binary file by running the following commands in the Embedded Command Shell:
    $ arm-altera-eabi-objcopy -O binary -R ARM_LIB_STACKHEAP application.axf application.bin

    $ mkimage -A arm -O u-boot -T standalone -C none -a 0x00100040 -e 0x00100040 -n “baremetal image” -d application.bin application-mkimage.bin

    $ arm-altera-eabi-objcopy -I binary -O ihex --adjust-vma -0xc0000000 application-mkimage.bin application.hex

    However, after recompiling the project in Quartus with the new binary file the same error appeared.

    I am not sure whether or not these most recent errors are related to similar issues compiling with the preloader image as mentioned above.

    As an FYI, the final project will eventually be open source so I can most likely provide additional information/files if it would be useful.