Hi,
Yes.
The 2nd ticket actually refer to same question. (I thought I have deleted one of them. sorry)
https://forums.intel.com/s/question/0D70P000006FEt8/bug-in-intels-soc-fpga-eds-
And Yes. After uninstall 18.1 and install 16.1 , all issues were solved.
I did not try to uninstall 16.1 and install 18.1 again to see if there is no issue with 18.1 (after uninstall and install).
I still don't know why 18.1 have issues with the gettingstarted example from fpgawiki page.
It seems that the build-it example (in eds folder) are probably other project type (makefile or not makefile) than the type of project from the fpgawiki page (Getting-started page).
I actually had another problem before when I tried to run the example from start->altera->ds-5 console , I think peaple should be careful with that....
Seems that install create 2 console, which is quite confusing!!
- start->altera->ds-5 console -> with this build of example fails !
- start->Intel's FPGA 16.1-> SOC EDS Command shell <<--- ONLY THIS SHOULD BE USED
Thanks