EMAC drivers Agilex5

Hi Matt,

I like the idea of the 2nd one you suggested.

Looking into the EMAC interface provided by the Agilex5 HPS - I can see that the connections are GMII.

Would I be correct to say that to connect the two it would look like this (1Gbps):

    assign emac0_app_rst_reset_n_wire = rst_n;                  // Same reset as all other comonents in Qsys top level design
    //assign emac0_mac_tx_clk_i_wire = clk;                     // not used in 1/2.5 Gbps
    assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire;     // emac0 rx clock = emac1 tx clock
    assign emac0_mac_rxdv_wire = emac1_mac_txen_wire;           // emac0 data valid  = emac1 enable
    assign emac0_mac_rxer_wire = emac1_mac_txer_wire;           // emac0 rx error = emac1 tx error
    assign emac0_mac_rxd_wire = emac1_mac_txd_o_wire;           // emac0 data in =  emac1 data out
    //assign emac0_mac_col_wire = 1'b0;                         // unused since not using half duplex
    assign emac0_mac_crs_wire = 1'b1;                           // signal is never idle

With symmetrical design for emac1?

I suppose I just need to know how to feed in to each block correct clock, reset, enable and valid signals given that there is no PHY involved