Declarations for UART_MAX_LEN and log_buf (Cyclone V) missing while compiling

Hi,

May I know which version of Quartus and SoC EDS software are you using?

Btw have you tried running a simple bare metal application on your board?

Here is the link to get you started:

https://www.intel.com/content/www/us/en/programmable/documentation/lro1424280108409.html

Hi,

I am using 16.0 Version (Quartus, NIOS II SBT, SoC EDS) on Windows. I have tried with latest version 18.1 on Ubuntu 18.04 and Windows as well. All of the them produces the same errors. I have again attached the compiler output screenshot.

I have tried running simple applications, and they are working but I have no clue what's is getting wrong in this project. I just want to setup an HPS and FPGA on Cyclone V DE1-SoC Board with following functions:

-->The HPS must be able to use the LED and button that are directly connected to the HPS PORTION of the device [DE1-SoC Board]. Pressing the button should toggle the LED.

-->The HPS must be able to access the LEDs connected to the FPGA PORTION of the device and will be responsible for creating a strobing light effect on the upper 5 LEDs.

The program is not so long but it uses the printf function. The linker Image file is set to use the "cycloneV-dk-ram-hosted.ld" to access some of the host's functionality to print on the console.

I will be thankful if you can elaborate the function of alt_retarget_gnu.c file. I am not able to find it in the documentation. What is really going wrong in the compilation process??

Hi,

You may find the alt_retarget_gnu.c file here in your Quartus Installation file:

"\intelFPGA\18.1\embedded\ip\altera\hps\altera_hps\hwlib\src\utils"

The C file contains minimal re target support to make printf function over UART for the GNU compiler.

Can you check your C file contains the UART_MAX_LEN, log_buf declarations?

Regards.

I know where the UART_MAX_LEN and log_buf are used in the source file but my question is: HOW SHOULD I DECLARE THEM? I dont know the functionality of both of these. There is nothing written in the documentation about them. Could you elaborate a little bit or point me to the documentation where it is written. Thanks

Is there anyone from Intel to answer my query? I am stuck in it since a month.

Hello,

I got the bare-metal application from here: https://github.com/sahandKashani/SoC-FPGA-Design-Guide/tree/master/DE1_SoC/DE1_SoC_demo.

I did following to include the HWlib in my project;

1- I used INCLUDE option of compiler to add the HPS HWlib HEADER FILES in my code.

2- I copied the HPS HWlib SOURCE FILES in my DS-5 project directory from altera/16.0/embedded/ip/altera/hps/altera_hps/hwlib/src.

Can you please describe how to add the HWlib to my project correctly?