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CAlex's avatar
CAlex
Icon for Contributor rankContributor
3 years ago

De10 HPS issue with FPGA interval timer IP

Hi, I'm now using the interval timer ip on HPS, I set the ip as general purposed timer. The timer is set to 100 ms and there is a timer_palus link to my fpga led[1] The setting is as shown: ...
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Alex

From your project top-level design. (Timer.v)

You have force the reset pin of the "Clock Source IP"

The "Clock Source IP" controls all the reset line of the other IP including the "Interval Timer IP"

By forcing the "Clock Source IP" in reset, it is putting the "Interval Timer IP" in reset.

Regards

Jingyang, Teh