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CAlex's avatar
CAlex
Icon for Contributor rankContributor
3 years ago

De10 HPS issue with FPGA interval timer IP

Hi, I'm now using the interval timer ip on HPS, I set the ip as general purposed timer. The timer is set to 100 ms and there is a timer_palus link to my fpga led[1] The setting is as shown: ...
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Alex

I managed to get the design running in simulation as I got a problem getting hands on to a devkit.

The design is not running is because of the reset.

The FPGA reset is coming from the "Clock Source IP" and it should not be force to always reset.

Please find the attached timer.v

Regards

Jingyang, Teh