Forum Discussion
CAlex
Contributor
3 years agoDe10 HPS issue with FPGA interval timer IP
Hi,
I'm now using the interval timer ip on HPS, I set the ip as general purposed timer.
The timer is set to 100 ms and there is a timer_palus link to my fpga led[1]
The setting is as shown:
...
tehjingy_Altera
Regular Contributor
3 years agoHi CAlex
Have you tried teh simulation? Is the design working in simulation?
Could you share me your quartus project? So I could try the design on my end.
Regards
Jingyang, Teh
CAlex
Contributor
3 years agoHi,
I haven't yet.
Could you tell me which simulation tool is available on quartus prime lite?
Also I attached my quartus project.
Thank you for your willing to help.
reguards.