Forum Discussion

MF28's avatar
MF28
Icon for New Contributor rankNew Contributor
4 years ago

Data Communication Time to high

Hello! I am currently using HPS and the FPGA together. I am communicating between them via the lightweight AXI Bridge. On the FPGA I also have LXDE Linux running. In order to test the maximum s...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


The access latency from lw_h2f bridge: for write access, it is about ~360ns, for read access, it is about ~420ns.


You can verify the result using a bare-metal code.


You can also use signal tap to monitor the real bus transaction and get the exact result.


MF28's avatar
MF28
Icon for New Contributor rankNew Contributor
4 years ago

Hello!
Thank you very much for those informations! These timings were very helpful, because they explain a lot about my timing.
I was able to optimize everything so far that the data rate is pretty much maxed out with Linux with 3.3 MByte/s .
Thanks for all the help!!!!