New Contributor
New ContributorI have tried all of the following examples from the installation folder:
Altera-SoCFPGA-HelloWorld-Baremetal-ARMCC.tar.gz
Altera-SoCFPGA-HelloWorld-Baremetal-GNU.tar.gz
Altera-SoCFPGA-HardwareLib-16550-CV-ARMCC.tar.gz
Altera-SoCFPGA-HardwareLib-16550-CV-GNU.tar.gz
And I've worked through the tutorial (and several others) numerous times.
The problem I run into with the tutorial is that it doesn't get updated with the information from my design. I'm working with a custom board, instead of the COTS development kit. When I get to the Run U-Boot SPL from Debugger step 9 (serial console output), the U-Boot SPL notices that the DRAM is a different size (512MB actual, while it is expecting 1GB, see attached) and stops. The ./board/altera/cyclone5-socdk/qts/sdram_config.h file has the proper parameters for my hardware (addr bits are 1 chip select, 3 bank, 10 column, 15 row, with 16-bit data width gives 2^29 = 512MBytes) so it seems the qts-filter.sh script is working fine. Building to the dev kit defaults (in a different directory) makes an sdram_config.h file with 1GB (1 cs, 3 ba, 10 col, 15 row, 40-bit ECC data gives 2^30 = 1GByte). How to I get the u-boot-spl to use the parameters for my design?
Also, I'm coming from years of designing with Xilinx devices, using baremetal for both microBlaze and ARM processors. The eclipse tools there allow one to specify a board support package for baremetal software- is there anything similar for the cyclone 5?
Regular ContributorHi,
I believe, the examples are tested using a dev kit, which has the 1GB DDR. For you custom board to execute on baremetal, you may need to change the entry starting point of the address for the 512MB SDRAM address space which is different from the 1024 MB. Also, change the DDR size in the device tree.
Let me recheck on how I did this last time.
Regular ContributorHi,
Please try to change the entry starting point of the address for the 512MB SDRAM address space in your application.
