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BrianSune_Froum
Contributor
ContributorCyclone V HPS bus - FPGA-to-SDRAM
Dear Intel, and all, Brian here and there is a very puzzling documenting on: https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/fpga-to-hps-sdram-access.html Based on the 256 bi...
BrianSune_FroumContributor
ContributorWith all due respect you had misinterpret my question.
The question is not above how to confirm.
It is above AXI3 settings the table from the document links are possibility wrongly labelled.
Perhaps you are try it using Quartus.
For AXI3 256 bit width bus how many interface can you used?
128 bit and 64 bit.
The question is still opened.
