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ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

cyclone v ddr3 hard ip with multiport

Hi Everyone, Im using cyclone V Soc evb board and Im trying to build example design for the ddr3 hard ip. we are using quartus version 18.1. memory clk: 400Mhz. ddr interface data width:32bit...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ram,


Thank you for submitting your question in Intel Community.


Can I have a look at the ddr3 example design that you are working with?


Regards,

Adzim