Occasional ContributorIs it possible to run the bare-metal application on Core 0 and Linux based monitoring application (no real-time feature required) on Core 1. If yes, the please can you kindly just elaborate the steps needed to achieve this.
Regular ContributorHi,
I'm not sure if Intel have the documentation to guide you, but there are some tutorials on bare metal for Cyclone V for utilizing multiple cores such as:
https://code-time.com/baremetal.html
There are also a similar post discussion using a Bare Metal on Core 0 and Linux on Core 1:
https://forums.intel.com/s/question/0D50P00003yyGYhSAM/boot-two-cores-in-cyclone-v-with-two-different-programs-or-os
Hope this helps.
Regards.
Regular ContributorHi,
I apologize, but Intel doesn't has the documentation regarding usage of Core 0 for baremetal and Core 1 for linux.
I would really suggest you check the first link on my previous reply.
https://code-time.com/baremetal.html
There, User Guide are available to guide you through and Read Me.txt that is included with important details.
You could try and sent some questions from the link, About Us > Contact Us > Email Us > Info.
Regular ContributorHi,
Have you try the examples in the link i provided?
Occasional ContributorHello,
I have tried the examples and it works. The functions such as TSKsetCore and TSKcreate, which are used to set the core and assign the program snippet to run on the desired core, has its source code hidden, as obvioulsy, it is not open source I guess. These functions are the ones most interesting for me. As I can roughly guess, that here, the core 1 is assigned to run a specific block of code. Now, I have a simple question---As I dont want to use the SMP RTOS version just to assign the core 1 to do a specific task;--- I need to just know the following;
"How can I write a short sequence of instructions for Core#0 in bare-metal to inform core#1 of where to start executing the program?? "
If I know this answer, then I am through hopefully.
P.S: I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core 1 is held in reset after a system reset is issued (Cold or warm). After reset, Core 0 is allowed to execute instructions. I know how to release the core 1 from reset and it works perfectly. In DS5 using JTAG chain I could easily run two different programs on Core#0 & Core#1, but my question pertains to the bare-metal program running from SD card.
Occasional ContributorHow can I get premium technical support for Cyclone V FPGA devices? Could you please share the link
Regular ContributorHi,
Let me check with our internal team, I shall come back to you with the information.
Regular ContributorOccasional ContributorI could not see the FPGA products when I got to Intel Premium support page and fill the form.
