Cyclone V: Core 0: Bare-Metal, Core 1: Linux OS

Hello,

I have tried the examples and it works. The functions such as TSKsetCore and TSKcreate, which are used to set the core and assign the program snippet to run on the desired core, has its source code hidden, as obvioulsy, it is not open source I guess. These functions are the ones most interesting for me. As I can roughly guess, that here, the core 1 is assigned to run a specific block of code. Now, I have a simple question---As I dont want to use the SMP RTOS version just to assign the core 1 to do a specific task;--- I need to just know the following;

"How can I write a short sequence of instructions for Core#0 in bare-metal to inform core#1 of where to start executing the program?? "

If I know this answer, then I am through hopefully.

P.S: I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core 1 is held in reset after a system reset is issued (Cold or warm). After reset, Core 0 is allowed to execute instructions. I know how to release the core 1 from reset and it works perfectly. In DS5 using JTAG chain I could easily run two different programs on Core#0 & Core#1, but my question pertains to the bare-metal program running from SD card.