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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
1 year ago
Solved

Custom board on Cyclone V HPS SDRAM preloader test

Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock...
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  • BrianSune_Froum's avatar
    BrianSune_Froum
    1 year ago

    The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
    The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
    UBOOT memory normal test also passed w/o any errors.

    So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

    No matter it is /w or /wo the board settings no drop no crash no stuck.

    So the case ends here.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


Yeah, sometimes the board is able to perform better than it suppose too.

The results you are seeing might differ from board to board.

That could be why the document stated that it is no supported.

We could not guarantee any performance issue if you are using the device out of the supported specification.


Regards

Jingyang, Teh