Forum Discussion
Aravindpb
New Contributor
New Contributorcould not create the verilog HDL file
i am using the altera 5CGXFC7C62317N , when try to create the verilog HDL file quartus showing some error like(Error (275069): Design file contains illegal characters for Verilog HDL) i dont know w...
Abe
Frequent Contributor
Frequent ContributorWhy do you need to convert the BDF to Verilog? Does the project compile (Analysis, Elaborate, Fitter , TIming Analysis) without errors? From the screenshots it looks like the compile process goes through.
Can you archive the project and upload it here so that we can take a look. Can't find out the cause of the issue from the screenshots. Have you tried checking the generated verilog files to see if there are any illegal characters? Can you post the Verilog files here?
Aravindpbhai abe
problem is due to confidential i can't share any files to outside
project compiled sucessfully point which you added in the above there is no problem in compilation
facing this problem since two days plz let me know the solution abe
Thanks
Aravind p
