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Aravindpb's avatar
Aravindpb
Icon for New Contributor rankNew Contributor
6 years ago

could not create the verilog HDL file

i am using the altera 5CGXFC7C62317N , when try to create the verilog HDL file quartus showing some error like(Error (275069): Design file contains illegal characters for Verilog HDL) i dont know w...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Were you able to create a Quartus project for the Cyclone V GX chip? Do you get this error when running the Quartus flow ?

The error states that the design file you created has illegal characters. Can you post the code here so that we can check it.?

Are you creating the design using the Block diagram edit BDF file. If so, delete the existing .v files, and then try compiling again. You could also try a clean of the project via the Project menu -> Clean Project.

Aravindpb's avatar
Aravindpb
Icon for New Contributor rankNew Contributor
6 years ago

Hai Abe

Thank you for your reply as per your instruction tried the points what you tell in previous msg but the thinks are getting again error

I created the design using the Block diagram edit BDF file and also deleted the existing .v file and tried once again also but the same error is appering as well as cleared my project via project menu-> clean project same error is appering on the screen

for more information i have provided screenshots in below plz go through my snaps

let me know the solutions

Thanks ,

Aravind p