could not create the verilog HDL file

Hai frdz thank you for your valuable reply , you two asked some more information about my questions . i provided detail asked in the below

using cyclone v 5CGXFC7C6F2317 family

compiler quartus prime 16.0 lite edition

I created the design using the Block diagram edit BDF file and also deleted the existing .v file and tried once again also but the same error is appering as well as cleared my project via project menu-> clean project same error is appering on the screen

for more information i provided my screen shorts what are the error appering

plz go through this screen shot let me know the solution