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Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
3 years ago

Cannot open bsp-editor with SoC EDS Pro 19.1 on Linux

Hello all, After having struggled for too long, I had to come here to seek for help. I want to work on SoC-FPGA projects with Intel Arria 10 board: Terasic HAN Pilot , which for information, an...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


In theory, how the old flow partially works is that, FPGA is programmed to the board and user can be in FPGA user mode, then it will boot the HPS and you will see the U-boot.


After all steps were done in the old flow, you add the .hex of your U-boot into the OCRAM of your FPGA in the memory initialization tab and re-compile your project to get the new .sof.


Before that, you might need to edit and change the device tree and U-boot settings to match your settings when you set the HPS IP to boot from FPGA signal = enabled.