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Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
3 years ago

Cannot open bsp-editor with SoC EDS Pro 19.1 on Linux

Hello all, After having struggled for too long, I had to come here to seek for help. I want to work on SoC-FPGA projects with Intel Arria 10 board: Terasic HAN Pilot , which for information, an...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


I am back, so boot from FPGA for new bootloader flow is currently not supported. But you are opt to use the old flow and see what you can do with the latest bootflow.


If it had worked for you, from my side, for HPS part, it needs to boot to U-boot this valids the HPS, for the FPGA you're basically programs the FPGA then it will boots the HPS after.


So you may check by enabling the bridges in U-boot then checks the FPGA addresses in U-boot.


For resets of HPS: If the HPS is reset the FPGA must be re-programmed.


Since the feature is currently not supported for our new bootloader, we may only provide best support to you for your issue.


Do you have any further questions or any questions that is still in unanswered?