Cannot open bsp-editor with SoC EDS Pro 19.1 on Linux

Hello EBERLAZARE_I_Intel,

Thanks for your prompt response, take the time you need for getting the feedback.

Ok, so I better understand why this could not work.

Then I should explain the whole picture. I use in my project the Intel JESD204B IP (under evaluation licence) which allows me to compile project and to use time-limited.sof FPGA programming file.

Problem with this is that I have HPS / FPGA project so I either need to :

- Reboot HPS once FPGA is programmed with .sof (which is done with boot HPS from FPGA)

- Program FPGA during the HPS boot flow (which is commonly done with .rbf file put in SD card)

So far I always used the 1st solution since we are not allowed to convert time-limited.sof to a time-limited.rbf.

Maybe I am not aware of other solutions existing to boot HPS from Quartus programmer or anything else? Or more generally, how to test Arria 10 HPS / FPGA projects (meaning, to fully validate the functioning of FPGA and HPS parts) that include evaluation licensed IP?

Looking forward to hearing from you,