Can anyone verify for me the following code for 32-bit calculator in verilog using FSM? 4 operation- +,-,*,/ Works on DVS protocol

Regular Contributor

7 years ago

Hi Dhaivat,

People in Intel community are not going to write code for you, but they will help you to understand or resolve the issue you are having. . .

Please refer the below steps & try to create testbench with appropriate test inputs & verify the design using simulation waveforms

1. First create testbench & instantiate the design in it & eventually compile the testbench in simulation tool(ModelSim) as shown in below link,

2. Another way : Go to 'Processing' -> 'Start' -> 'Start Test Bench Template Writer'

Check'Message window' for .vt or .vht file generated in projet directory

3. For NativeLink Simulation use testbench generated in either step(1) or step(2) & try to simulate as shown in below link,

4. One more way to simulate design using vector waveform files refer the link below,

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas

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