New ContributorCan anyone verify for me the following code for 32-bit calculator in verilog using FSM? 4 operation- +,-,*,/ Works on DVS protocol
module calc (
input [7:0] inpA ,
input [7:0] inpB ,
input [01:0] inpOpType ,
output[15:0] outC ,
input iValid ,
output iStall ,
input oStall ,
output oValid ,
input clk ,
input rstn
) ;
//----------------------------------------------------------------------
parameter ST_IDL = 1'b0 ;
parameter ST_STALL = 1'b1 ;
reg inp_dstall_r, oup_dval_r, lat_inp_r ;
reg inp_dstall_s, oup_dval_s, lat_inp_s ;
reg st_cur, st_nxt ;
reg [31:0] store_a, store_b, oup_s ;
reg [01:0] store_ctrl ;
//----------------------------------------------------------------------
// FSM
//----------------------------------------------------------------------
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;
reg [1:0] cs, ns;
always @ (posedge clk)
begin
if(rstn)
cs <= s0;
else
cs <= ns;
end
//----------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if(!rstn) begin
lat_inp_r <= 1'b0 ;
inp_dstall_r <= 1'b0 ;
st_cur <= ST_IDL ;
oup_dval_r <= 1'b0 ;
end
else begin
inp_dstall_r <= inp_dstall_s ;
lat_inp_r <= lat_inp_s ;
st_cur <= st_nxt ;
oup_dval_r <= oup_dval_s ;
end
end
//----------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
ns = s0;
case (cs)
s0 : if (!store_ctrl) ns = s1;
s1 : if (store_ctrl) ns = s2;
else ns = s1;
s2 : if (store_ctrl) ns = s3;
else ns = s1;
s3 : if (!store_ctrl) ns = s1;
endcase
end
always @(posedge clk) begin
if(lat_inp_s) begin
store_a <= inpA ;
store_b <= inpB ;
store_ctrl <= inpOpType ;
end
end
//----------------------------------------------------------------------
always @* begin
if(store_ctrl == 2'b00) oup_s = store_a + store_b ;
else if(store_ctrl == 2'b01) oup_s = store_a - store_b ;
else if(store_ctrl == 2'b10) oup_s = store_a * store_b ;
else if(store_b == 0) oup_s = 0 ;
else oup_s = store_a / store_b ;
end
//----------------------------------------------------------------------
assign iStall = inp_dstall_r ;
assign oValid = oup_dval_r ;
assign outC = oup_s ;
//----------------------------------------------------------------------
endmodule
