Hi,
Sorry for the late response. I tried to gather images for this question.
My goal is to build my own bare metal app which being loaded from qspi into sdram by preloader and uses HWLib.
my problem is that only the preloader is loaded from qspi and not my app.
These are the steps I've taken so far:
1. Create a project for HWLib and a seperate "hello" project which uses the HWLib.
- I created my project using Arm compiler 5 (DS built in) and
the instructions from section 1.6.1.1:
https://www.intel.com/content/www/us/en/docs/programmable/683211/current/create-project-22401.html
- I use the same scatter file as appears in section 1.6.3.1 (the upper one):
https://www.intel.com/content/www/us/en/docs/programmable/683211/current/create-a-new-scatter-file-to-locate.html
- The projects is compiles succesuflly and .bin is generated from .axf using fromelf.
- 1.PNG - 4.PNG shows some of the settings and compilaion output
2. After the app .bin file is ready I used the following mkimage command to add header for my .bin app:
mkimage -A arm -O u-boot -T standaone -C none -a 0x02000000 -e 0x02000000 -n "alg_baremetal" -d alg.bin alg.img
- 5.PNG
3. I created and compiled the preloader and flashed both preloader and alg.img using instructions
from:
https://www.intel.com/content/www/us/en/docs/programmable/683265/current/booting-from-qspi-flash.html
- I used the handoff folder for generating the BSP and preloader from here:
https://www.rocketboards.org/foswiki/Documentation/WS1IntroToAlteraSoCDevices
(the ALTERA AV SOC files)
- flashed alg.img and not alg.bin
- 6.PNG for flashing alg.img
4. boot log:
[15:29:51:390] U-Boot SPL 2013.01.01 (Mar 02 2023 - 16:50:19)␍␊
[15:29:51:390] BOARD : Altera SOCFPGA Arria V Board␍␊
[15:29:51:390] CLOCK: EOSC1 clock 25000 KHz␍␊
[15:29:51:390] CLOCK: EOSC2 clock 25000 KHz␍␊
[15:29:51:390] CLOCK: F2S_SDR_REF clock 0 KHz␍␊
[15:29:51:390] CLOCK: F2S_PER_REF clock 0 KHz␍␊
[15:29:51:390] CLOCK: MPU clock 1050 MHz␍␊
[15:29:51:390] CLOCK: DDR clock 533 MHz␍␊
[15:29:51:390] CLOCK: UART clock 100000 KHz␍␊
[15:29:51:390] CLOCK: MMC clock 50000 KHz␍␊
[15:29:51:390] CLOCK: QSPI clock 350000 KHz␍␊
[15:29:51:390] RESET: COLD␍␊
[15:29:51:390] SDRAM: Initializing MMR registers␍␊
[15:29:51:390] SDRAM: Calibrating PHY␍␊
[15:29:51:390] SEQ.C: Preparing to start memory calibration␍␊
[15:29:51:417] SEQ.C: CALIBRATION PASSED␍␊
[15:29:51:417] SDRAM: 1024 MiB␍␊
[15:29:51:417] SDRAM: Initializing SDRAM ECC␍␊
[15:29:52:872] SDRAM: ECC initialized successfully with 1464 ms␍␊
[15:29:52:872] SDRAM: ECC Enabled␍␊
[15:29:52:898] SF: Read data capture delay calibrated to 3 (0 - 7)␍␊
[15:29:52:898] SF: Detected N25Q512 with page size 65536, total: 67108864␍␊
Thank you very much for your patience.
Occasional Contributor
