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GBraj's avatar
GBraj
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Arria 10 SoC FPGA Remote update via HPS/linux

Hello everybody, we are using an Intel Arria 10 SX with HPS on a custom board (10AS057K4F40E3SG with Quartus Pro 22.4). The boot flow is as specified on Rocketboards website (https://www.rocketboar...
  • aikeu's avatar
    aikeu
    3 years ago

    Hi GBraj,


    Double config can solve the some issue related DDR issue in A10. So it will be required.


    Thanks.

    Regards,

    Aik Eu


GBraj's avatar
GBraj
Icon for New Contributor rankNew Contributor
3 years ago

Hi Aik,

now the changes are working as intended: a full reprogram (periph+core) of the FPGA is triggered on every reboot command by linux and also with the HPS cold reset button. Probably a more "elegant" solution would be an ifdef clause linked to a certain defconfig during the build stage of U-boot, in order to keep the compatibility with other boot sources (EPCQ/etc)...but it works.

About the double programming of peripherals, I've found some references in the official source code: https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/misc_arria10.c#L142-L157

Could you please investigate internally with your colleagues if double periph config is needed on Arria 10 SoC?

Regards.