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Adi-41's avatar
Adi-41
Icon for New Contributor rankNew Contributor
3 years ago

Arria 10 DDR3 Emif calibration issues

Hi everyone, In a new project we proposed to use Arria 10 10AX016E3F27I2SG FPGA. As external memory we use the AS4C128M8D3B 1Gb DDR3 SSDRAM. All our attempts to control the DDR3 correctly have ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Adi,


I have checked and compiled the design at my side.

There are a few EMIF IP parameters that I have changed by following the memory datasheet.

  • Memory CAS latency setting to '11'
  • tRCD and tRP to '13.75'

Can you test with these changes?


Other than that, can you test with the EMIF example design that can be generated from the IP parameter?

The EMIF example design can run a test pattern that handle by the traffic generator.

We can check the test by monitoring the status signal of the traffic generator.

  • tg_0_traffic_gen_pass
  • tg_0_traffic_gen_fail


I can provide the EMIF example design if you need.

Please let me know if you need that help.


Regards,

Adzim