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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Any Cyclone V soc bare metal startup project settings available?

Hi, I successfully ran the sample on the rocketboards, now I want to make my own project, do you guys have any setting guide for that? Reguards.
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi CAlex,


If you wanto run from ddr you will need the SPL(u-boot-splx4.sfp) to init the ddr first.

To boot from ddr you will need to run the below cmd when makding your application code:

Refer to the section(Software Examples) with the table https://github.com/altera-opensource/intel-socfpga-hwlib

if ddr the cmd will be:

make SEMIHOSTED=0 MEMORY=ddr


Thanks.

Regards,

Aik Eu





CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Hi,

Yes I downloaded/ran the u-boot-spl and .bin file to _bss_end. And the console said it was succeed,

After that I

1. disconnect the preloader ds debug(connect only),i didn't find u-boot-splx4.sfp on my u-boot-socfpga/spl/ file, could you please tell me where to find it?

2. connect the program debug(start from entry point) with the scatter file cvav-ddr.scat (and built/link the interrupt_armcc.s) entrypoint is 0x0100_0000 with the Vector

I have the other debug started from 0x0200_0000 without Vector

3. Then the error showed up.

Reguards.