Contributor
ContributorHi,
I managed to worked through that problem, it seems the SOCEDS 20.1 didn't support the WSL2, so I ran it under MSYS2 MSYS.
The other issue came to me :
When I ran the cycloneV FPGA GNU examples with ddr and semihosting the debug stopped at order line: B _mainCRTSartup:
I didnt set any breakpoint or watchpoint. The socfpga I used is coming from GHRD with noi change.
Reguards.
ContributorWhen I restarted all the system it came to normal again.
Here is the solution from ARM experts:
You need to get into the breakpoint view to do some settings to avoid this issue.
