Contributor
Frequent ContributorHi K606,
Sorry for the delay in responding to this thread. Based on the error and your explanation on jic file is working, with the assumption of the same sof file is used for the jic generation as well (not due to mismatch handoff settings), the only difference that I could think of is that the with the sof file, the configuration is volatile/not persistent in FPGA SRAM and lost after every reset or power cycle, thus error will occur when reboot/power cycle and FPGA configuration is not there.
Along these lines
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... Loading Environment from UBI... "Synchronous Abort" handler, esr 0x96000010, far 0x108d2000
1st warning usually non fatal, just indicating cannot load or no sd card
2nd warning is indicating loading environment from NAND/UBI filesystem but fails together with the synchronous abort indicating ARM CPU tries to access the address that is not valid , most likely on the FPGA register side bridges or peripherals
As for JIC , it is stored in persistent memory and loaded automatically every reset/reboot thus HPS is able to boot successfully
Thanks
Regards
Kian
