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MesbahKarim's avatar
MesbahKarim
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3 years ago

Agilex Ftile is not asserting tx_ready after the reset sequence (tx_rreset/tx_reset_ack)

Hello, I build my controller model to Agilex F-tile transceiver. Please see the configuration below for F-tile and simulation waveform. Xcvr is asserting tx_reset/tx_reset_ack and rx_reset/rx_r...
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi Mesbah,


Can you please share your project, so that I can look into the issue.


Thank you

Kshitij Goel


MesbahKarim's avatar
MesbahKarim
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3 years ago

Hi Goel,

Sorry for the late response. I was waiting for Quartus 23.1 to release and use it We just received it and IT is i

Do you want whole project? I sent you the F-Tile configuration. My project includes our IP blocks.

This is not loopback model. Our IP has also Serdes. This is a communication between to Serdes.

We want F-Tile transceiver is ready to communicate with another Serdes. Do you have any example design of that configuration that I mentioned in my first correspondence? even loopback is also fine. Please share with me. Quartus project have a few example_design. I can not configure with my configuration and generate example design. If you have please share with me

Thanks

Mesbah